1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device to which successive accesses can be made.
2. Description of Related Art
Semiconductor memory devices represented by DRAM (Dynamic Random Access Memory) are generally configured such that a memory cell array is connected via an I/O line to an input/output circuit. During a write operation, write data is supplied from the input/output circuit via the I/O line to the memory cell array, and during a read operation, read data read from the memory cell array is supplied via the I/O line to the input/output circuit.
FIG. 41 is a circuit diagram showing a configuration of principal parts of a conventional DRAM.
The DRAM shown in FIG. 41 includes a memory cell array 1 that includes word lines WL0, WL1, . . . , bit line pairs BL0, BL1, . . . , and memory cells MC arranged at intersections of the word lines with the bit lines. A sense amplifier 2 is connected to each of the bit line pairs BL0, BL1, . . . . The sense amplifier 2 is connected via a corresponding column switch 5 to an I/O line LIO. Column select signals YS0, YS1, . . . that are output signals of column select drivers 4 are supplied to the respective column switches 5, so that any one of the switches is brought into on state.
The I/O line LIO is a wiring for transmitting complementary differential signals and connected to an input/output circuit 20. The input/output circuit 20 includes a write buffer 10 that supplies write data provided through a write bus WBUS to the I/O line LIO and a read amplifier 6 that supplies read data provided through the I/O line LIO to a read bus RBUS.
An operation of the DRAM with the configuration described above is described.
First, when a word driver 3 drives any one of the word lines WL0, WL1, . . . , the word line WL0 for example, signal charges stored in the memory cells MC are read to the respective bit line pairs BL0, BL1, . . . . Because the amounts of signals appearing in the bit line pairs BL0, BL1, . . . are small, however, the signals are amplified by the respective sense amplifiers 2. The bit line pairs BL0, BL1, . . . are driven in full amplitude, the selected memory cells MC are rewritten to be in a full level, and the amplified signals are held by the sense amplifiers 2.
Next, any one of the column select signals YS0, YS1, . . . is activated by the corresponding column select driver 4, thereby turning on the corresponding column switch 5. Any one of the bit line pairs is thus connected to the I/O line LIO.
However, the signal level read to the I/O line LIO is also small. Accordingly, to perform a read operation, the signal read to the I/O line LIO is further amplified by the read amplifier 6, latched at a hold circuit 7, and then outputted via a tri-state buffer 8 to the read bus RBUS. The read amplifier 6, the hold circuit 7, and the tri-state buffer 8 operate in synchronization with an activation signal RAE. The activation signal RAE is a timing signal during the read operation.
On the other hand, when a write operation is performed, write data supplied through the write bus WBUS is latched at a hold circuit 9 and then supplied to the I/O line LIO via the write buffer 10. The hold circuit 9 and the write buffer 10 operate in synchronization with an activation signal WBE. The activation signal WBE is a timing signal during the write operation. The write data provided to the I/O line LIO is supplied via a switched-on column switch 5 to any of the bit line pairs. The write data is thus forcibly overwritten in the sense amplifier 2 and this written data is to be written in the memory cells MC.
An operation timing when the write operation and the read operation are requested successively (write-to-read operation) is described next.
FIG. 42 is a timing diagram showing an operation timing when a write operation and a read operation are requested successively for the same address.
First, when a write request is issued at a time t1, write data D is supplied to the write bus WBUS after a predetermined period of time. At a time tWBE, the activation signal WBE is activated, so that the write data D is outputted to the I/O line LIO. The column select signal YS0 is then activated, so that the write data D is written in the corresponding bit line pair BL0. Next, when a read request is issued at a time t2, the data D written by the write request at the time t1 is read to the I/O line LIO. After a significant potential difference in the I/O line LIO, the activation signal RAE is activated at a time tRAE, so that read data D is read to the read bus RBUS.
When the write operation is completed within one clock cycle as described above, any data collision does not occur on the I/O line LIO and the bit line even if the write operation and the read operation are requested successively for the same address. Although not illustrated, when the read operation and the write operation are requested alternately and successively for the same address, when the write operation is requested more than twice consecutively for the same address, and when the read operation is requested more than twice consecutively for the same address, any data collision does not occur and accurate operations can be performed. That is, when the write operation or the read operation is completed within a clock cycle, the accurate operations can be performed no matter what accesses are requested. Accordingly, the I/O line LIO can be shared by the sense amplifiers 2 as shown in FIG. 41. The I/O line LIO literally serves as both an input and an output.
Recently, however, operations of memory devices have become complicated. Some cases that complicated calculations including coding are performed before write in a memory cell array will be probably increased. An example of such cases is a memory device having an ECC (Error Correcting Code) circuit incorporated therein. The write operation may not be completed within a clock cycle. In the case that the write operation cannot be completed within a clock cycle, when the write operation and the read operation are successively requested, the write operation cuts into the time that the subsequent read operation. Such a problem is described below in detail using a timing diagram.
FIG. 43 is a timing diagram showing an operation timing when the write operation and the read operation are successively requested (write-to-read operation) for different addresses in a memory that cannot complete the write operation in a clock cycle.
First, when a write request is issued first at the time t1, a calculation that takes a long time is performed. When the calculation is completed, write data D0 is supplied to the write bus WBUS. The activation signal WBE is then activated at the time tWBE, so that the write data D0 is outputted to the I/O line LIO. The column select signal YS0 is then activated and the write data D0 is written in the corresponding bit line pair BL0. When a read request is issued at the time t2, the corresponding column select signal YS1 is activated and read data D1 appears in the I/O line LIO. According to this example, the activation of the activation signal WBE at the time tWBE and the activation of the column select signal YS0 are naturally delayed from the write request at the time t1 by a calculation time. The column select signal YS1 rises when the write data D0 is being written in the bit line pair BL0 and the write data D0 is written even in the bit line pair BL1. The read data D1 from the bit line pair BL1 is thus affected by the write data D0 for BL0. Even if the read data D1 on the bit line pair BL1 is not inverted as shown in FIG. 43, the I/O line LIO is affected significantly by the write data D0. Accordingly, the value supplied to the read bus RBUS by the activation signal RAE that is activated at the time tRAE in response to the read request at the time t2 may be D0 not the expected D1. That is, incorrect data is read.
FIG. 44 shows an operation timing when the write operation and the read operation are successively requested (write-to-read operation) for the same address in the memory that cannot complete the write operation in a clock cycle.
The write operation is the same as the operation described with reference to FIG. 43. That is, in response to the write request at the time t1, the write data D is transmitted successively to the write bus WBUS, the I/O line LIO, and the bit line pair BL0. While the write data is being written in the bit line pair BL0, however, the column select signal YS0 rises in response to the read request at the time t2. When the activation of the activation signal RAE at the time tRAE is performed during an activating period of the write buffer 10 (WBE=H), the data D can be read correctly. When the activation of the activation signal RAE is performed after the activating period of the write buffer 10 (WBE=L) as shown in the example of FIG. 44, the bit line pair BL0 in amplitude is connected to the I/O line LIO and thus the potential of the I/O line LIO is drawn. Accordingly, when the signal amount on the I/O line LIO is small and the activation signal RAE is activated at the time tRAE, the correct value cannot be read to the read bus RBUS (X: undefined).
As shown in FIG. 43, when the write operation goes on into the subsequent read operation in the write-to-read operation for different addresses, it suffices that the I/O line LIO is divided into a data line for write and a data line for read. Data collisions between the write data and the read data are thus eliminated. Similarly, it suffices that the column select signal YS is divided into a column select signal YS1 for write and a column select signal for read. Such I/O division is also described in “Symposium on VLSI Circuits, Dig of Tech. Papers” (pp. 17-18, 1990, Y. NAKAGOME et al.) and “Super LSI Memory” (ITOH Kiyoo, published by Baihukan, November 1994, ISBN4563036099, pp. 165-167).
However, problems about the write-to-read operation for the same address shown in FIG. 44 cannot be solved only by the I/O division. Thus, the only way to perform correctly the write-to-read operation requested for the same address is to set a clock cycle to be longer, which hinders a high speed operation. Accordingly, a semiconductor memory device that can perform correctly the write-to-read operation for the same address and realize a high speed operation is desired.
When the write operation that takes time to start is required, a data collision occurs not only in the write-to-read operation but also in the write-to-write operation. Two kinds of write operations, that is, the write operation that takes time to start because of a calculation and the write operation that can start promptly depending on clocks as usual are provided. In this case, the write operation that takes time to start overlaps the next cycle, that is, the read operation in the next cycle or the write operation that can start promptly in response to clocks in the next cycle. Particularly when the write operation that takes time to start overlaps the write operation that can start promptly in response to clocks, this problem cannot be solved by dividing the I/O line into a data line for write and a data line for read. Such a problem occurs in the clearest manner when the write cycle is configured by two kinds of write operations, that is, the write operation that can start promptly in response to clocks and the write operation that takes time to start. Accordingly, a semiconductor memory device that can perform correctly the write-to-write operation for different addresses and for the same address and realize a high speed operation is also desired.